1. Field of the Invention
The present invention relates to semiconductor structures and fabrication methods thereof, and, more particularly, to a semiconductor structure having conductive pillars and a fabrication method thereof.
2. Description of Related Art
Electronic products are becoming lighter, thinner and smaller, as well as developed for high performance and multi-functionality. There are various types of semiconductor chip packages, such as wire bonding type packages, flip-chip type packages and so on. Compared with wire bonding type packages, flip-chip type packages are advantageous in reducing the overall volume of semiconductor devices.
A fabrication method of a flip-chip type package generally involves electrically connecting an active surface of a chip to conductive pads of a packaging substrate through a plurality of conductive bumps, and filling an underfill between the active surface of the semiconductor chip and the substrate for encapsulating the conductive bumps. Therein, the material of the conductive bumps greatly affects the flip-chip alignment accuracy.
U.S. Pat. Nos. 7,863,740 and 7,804,173 disclose methods for electrically connecting a semiconductor chip with a packaging substrate through copper pillars.
Referring to FIG. 1A, a semiconductor chip 10 having at least an electrode pad 100 is provided. The outer surface of the semiconductor chip 10 is made of a silicon nitride layer, which has an opening for exposing the electrode pad 100, respectively.
Then, a dielectric layer 12 is formed on the silicon nitride layer 101 and around the wall of the opening of the silicon nitride layer 101. Subsequently, a titanium layer 11 is formed to cover the entire surface of the dielectric layer 12 and the electrode pad 100. Further, a copper layer 13 is formed to cover the entire surface of the titanium layer 11.
Referring to FIG. 1B, a resist layer 14 is formed on the copper layer 13 and an open area 140 is formed in the resist layer 14 for exposing a portion of the copper layer 13. Then, a copper pillar 15 is formed on the exposed portion of the copper layer 13 and a solder material 16 is formed on a top surface of the copper pillar 15.
Referring to FIG. 1C, the resist layer 14 is removed to expose a portion of the copper layer 13.
Referring to FIG. 1D, using the copper pillar 15 as an etch stop layer, an etching process is performed to remove the exposed portion of the copper layer 13 and the titanium layer 11 under the exposed portion of the copper layer 13. Thereafter, a solder bump can be formed on the copper pillar 15 and the solder material 16, and then a reflow process can be performed so as to form a conductive bump electrically connecting the chip 10 and a packaging substrate (not shown).
Since the copper pillar 15 does not deform during the reflow process, melting and collapsing of the copper pillar 15 can be prevented, thereby avoiding position deviation of the chip 10 and increasing position alignment accuracy of the chip 10.
However, since the etching process using an etching solution is isotropic, when the copper layer 13 and the titanium layer 11 under the copper layer 13 are partially removed by etching, an undercut of the titanium layer 11 can occur, as shown at position K of FIG. 1D, thus resulting in an insufficient support for the copper pillar 15 and reducing the reliability of the conductive bump.
Therefore, there is a need to provide a semiconductor structure and a fabrication method thereof so as to overcome the above-described drawback.